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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7002 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 lc 2 mos gsm baseband i/o port functional block diagram 10-bit dac 10-bit dac 2.5v reference reference output buffer ad7002 i tx q tx ref out i rx q rx aux flag clk2 av agnd tx sleep tx data three-state enable rx data (i data) aux data aux clk aux latch rx sleep1 rx sleep2 gmsk pulse shaping rom dd dgnd dv dd 4th order bessel low-pass filter 4th order bessel low-pass filter aux dac 1 aux dac 2 aux dac 3 9-bit dac 10-bit dac 8-bit dac 16-bit shift register clk1 mzero s-d modulator s-d modulator tx clk rx sync i channel digital fir filter offset register q channel digital fir filter offset register receive channel serial interface rx clk rate mode cal switch-cap filter switch-cap filter i/q (q data) features single +5 v supply transmit channel on-chip gmsk modulator two 10-bit d/a converters analog reconstruction filters power-down mode receive channel two sigma-delta a/d converters fir digital filters on-chip offset calibration power-down mode 3 auxiliary d/a converters power-down modes on-chip voltage reference low power 44-lead pqfp applications gsm pcn general description the ad7002 is a complete low power, two-channel, input/ output port with signal conditioning. the device is used as a baseband digitization subsystem, performing signal conversion between the dsp and the if/rf sections in the pan-european telephone system (gsm). the transmit path consists of an onboard digital modulator, containing all the code necessary for performing gaussian mini- mum shift keying (gmsk), two high accuracy, fast dacs with output reconstruction filters. the receive path is composed of two high performance sigma-delta adcs with digital filtering. a common bandgap reference feeds the adcs and signal dacs. three control dacs (aux dac1 to aux dac3) are in- cluded for such functions as afc, agc and carrier signal shap- ing. in addition, aux flag may be used for routing digital control information through the device to the if/rf sections. as it is a necessity for all gsm mobile systems to use the lowest power possible, the device has power-down or sleep options for all sections (transmit, receive and auxiliary). the ad7002 is housed in 44-lead pqfp (plastic quad flatpack).
C2C rev. b ad7002Cspecifications 1 parameter ad7002a units test conditions/comments adc specifications resolution 12 bits rx sleep = 0 v, tx sleep = v dd signal input span v ref /2 volts biased on v ref (2.5 v) sampling rate 13 msps output word rate 270.8 khz rate 0 541.7 khz rate 1 accuracy integral 1 lsb typ differential 2 0 bias offset error 6.5 lsb max after external calibration; mzero low 8 lsb typ after internal calibration; mzero high input resistance (dc) 300 k w typ input capacitance 10 pf typ dynamic specifications input frequency = 67.7 khz dynamic range 64 db typ signal to (noise+distortion) 62 db min gain error 0.5 db max input frequency = 67.7 khz, w.r.t. 2.5 v gain match between channels 0.15 db max input frequency = 67.7 khz filter settling time 47 m s typ frequency response 0 khzC100 khz 0.05 db max 110 khz C0.8 db max 122 khz C3.0 db max 200 khz C66 db max 400 khzC6.5 mhz C72 db max absolute group delay 23 m s typ group delay between channels (0 khzC120 khz) 5 ns typ coding twos complement power-down option yes rx sleep = v dd , independent of transmit transmit dac specifications resolution 10 bits rx sleep = v dd , tx sleep = 0 v number of channels 2 update rate 4.33 msps 16 3 oversampling of the bit rate dc accuracy integral 0.7 lsb typ differential 1.0 lsb typ output signal span v ref /2 volts centered on v ref nominal (100 k w /20 pf load) output signal full-scale accuracy 1 db max w.r.t. 2.5 v offset error 25 mv max 10 0000 0000 loaded to dac i tx & q tx gain matching 0.15 db max absolute group delay 10 m s typ measured at 67.7 khz group delay linearity (0 khzC120 khz) 30 ns typ each channel, 10 khz < f out < 100 khz phase matching between channels 0.5 typ generating 67.7 khz sine waves gmsk spectrum mask 3 100 khz C3 db min 200 khz C32 db min 250 khz C35 db min 400 khz C63 db min 0.6 mhz C71 db min 4.3 mhz C63 db min 6.5 mhz C63 db min gmsk phase trajectory error 3 2 rms max 6 peak max maximum phase effect instance 3 9 m s typ output impedance i tx 120 w typ q tx 120 w typ gmsk rom yes contains gmsk coding, four-bit impulse response power-down option yes tx sleep = v dd , independent of receive (av dd = +5 v 6 10%; dv dd = +5 v 6 10%; agnd = dgnd = 0 v, f clk1 = f clk2 = 13 mhz; t a = t min to t max , rx sleep 1 = rx sleep 2 = tx sleep = dv dd , unless otherwise noted)
C3C rev. b ad7002 parameter ad7002a units test conditions/comments auxiliary dac specifications aux1 aux2 aux3 resolution 9 10 8 bits dc accuracy integral 2 2 1 lsb max differential 1 1 1 lsb max guaranteed monotonic offset error 2 4 1 lsb max gain error 4 4 2 lsb max lsb size 4.88 2.44 9.77 mv typ output signal span 0 to v ref 0 to v ref 0 to v ref volts unloaded output output impedance 10 10 10 k w max aux dacs have unbuffered resistive outputs 888 k w typ coding binary binary binary power-down yes yes yes power-down is implemented by loading all 1s or all 0s reference specifications refout, reference output 2.4/2.6 v min/v max r l = 100 k w , c l = 1 nf refout, reference output @ +25 c 2.5 v typ r l = 100 k w , c l = 1 nf reference temperature coefficient 100 ppm/ c typ reference variation 4 10 mv max output impedance 60 w typ logic inputs v inh , input high voltage v dd C 0 9 v min v inl , input low voltage 0.9 v max i inh , input current 10 m a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage 4.0 v min |i out | 200 m a v ol , output low voltage 0.4 v max |i out | 1.6 ma power supplies av dd 4.5/5.5 v min/v max dv dd 4.5/5.5 v min/v max i dd all sections active 30 ma max adc and auxiliary paths active 5 18 ma max tx sleep = v dd 15 ma typ transmit dac and aux paths active 6 14 ma max rx sleep 1 = rx sleep 2 = v dd 11 ma typ auxiliary path only active 5, 6, 7 2 ma max tx sleep = rx sleep 1 = rx sleep 2 = v dd notes 1 operating temperature range: a version: C40 c to +85 c. 2 unmeasurable: sigma-delta conversion is inherently free of differential nonlinearities. 3 see terminology. 4 change in reference voltage due to a change in tx sleep or rx sleep modes. 5 measured while the digital inputs to the transmit interface are static. 6 measured while the digital inputs to the receive interface are static. 7 measured while the digital inputs to the auxiliary interface are static. specifications subject to change without notice.
ad7002 C4C rev. b terminology absolute group delay absolute group delay is the rate of change of phase versus fre- quency, d q /df. it is expressed in microseconds. bias offset error this is the offset error (in lsbs) in the adc section. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the dac or adc. dynamic range dynamic range is the ratio of the maximum output signal to the smallest output signal the converter can produce (1 lsb), ex- pressed logarithmically, in decibels (db = 20log 10 (ratio)). for an n-bit converter, the ratio is theoretically very nearly equal to 2 n (in db, 20nlog 10 (2) = 6.02n). however, this theoretical value is degraded by converter noise and inaccuracies in the lsb weight. full-scale accuracy this is the measure of the adc full-scale error after the offset has been adjusted out. gain error this is a measure of the output error between an ideal dac and the actual device output with all ls loaded after offset error has been adjusted out and is expressed in lsbs. in the ad7002, gain error is specified for the auxiliary section. gain matching between channels this is the gain matching between the itx and qtx channel and is expressed in dbs. gmsk spectrum mask this is the combined output spectrum of the i and q analog outputs when transmitting a random sequence of data bits on the ad7002 transmit channel. 100 200 250 400 600 1800 4300 C3 C32 C35 C63 C71 C71 C63 amplitude C db frequency C khz C63 6500 ad7002 transmit gmsk spectrum mask absolute maximum ratings 1 (t a = +25 c unless otherwise noted) dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v digital input voltage to dgnd . . . . C0.3 v to dv dd + 0.3 v analog input voltage to agnd . . . . C0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range industrial plastic (a version) . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at those or any other conditions above those listed in the operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. pin description aux flag aux latch aux clk aux data mzero nc rx sleep1 test2 nc rx sleep2 cal tx sleep tx data clk2 tx clk dv dgnd nc clk1 test1 nc nc 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 pin 1 identifier ad7002 pqfp top view (not to scale) i rx test4 q rx i tx refout q tx agnd av aux dac2 aux dac3 aux dac1 rate mode test3 dv dgnd nc rx data (idata) rx sync rx clk 3-state enable nc = no connect dd dd dd i/q (qdata) ordering guide temperature package package model range description option AD7002AS C40 c to +85 c plastic quad flatpack s-44 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7002 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7002 C5C rev. b gmsk phase trajectory error this is a measure of the phase error between the transmitted phase of an ideal gmsk modulator and the actual phase trans- mitted by the ad7002, when transmitting a random sequence of data bits. it is specified as a peak phase error and also as an rms phase error. group delay linearity the group delay linearity, or differential group delay, is the group delay over the full band relative to the group delay at one particular frequency. the reference frequency for the ad7002 is 1 khz. group delay between channels this is the difference between the group delay of the i and q channels and is a measure of the phase matching characteristics of the two. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the dac or adc transfer function. maximum phase effect instance this is the time at which a transmitted data bit will have its maximum phase change at the itx and qtx outputs (see fig- ure). this time includes the delay in the gmsk modulator and in the analog low-pass filters. maximum phase effect instance is measured from the tx clk falling edge, which latches the data bit, to the itx and qtx analog outputs. 90 0 ? 9 m s data bit clocked in by txclk maximum phase effect instant transmitted phase for one data bit 45 transmit channel maximum phase effect instance output rate this is the rate at which data words are made available at the rx data pin (mode 0) or the idata and qdata pins (mode 1). there are two rates, depending on whether the de- vice is operated in rate0 or rate1. offset error this is the amount of offset, w.r.t. v ref in the transmit dacs and the auxiliary dacs and is expressed in mvs for the trans- mit section and in lsbs for the auxiliary section. output impedance this is a measure of the drive capability of the auxiliary dac outputs and is expressed in k w s. output signal span this is the output signal range for the transmit channel section and the auxiliary dac section. for the transmit channel the span is 1.25 volts centered on 2.5 volts, and for the auxiliary dac section it is 0 to +v ref . output signal full-scale accuracy this is the accuracy of the full-scale output (all 1s loaded to the dacs) on each transmit channel measured w.r.t. 25 v and is expressed in dbs. phase matching between channels this is a measure of the phase matching characteristics of the i and q transmit channels. it is obtained by transmitting all ones and then measuring the difference between the actual phase shift between the i and q outputs and the ideal phase shift of 90 . sampling rate this is the rate at which the modulators on the receive channels sample the analog input. settling time this is the digital filter settling time in the ad7002 receive section. on initial power-up, or after returning from the sleep mode, it is necessary to wait this amount of time to obtain use- ful data. signal input span the input signal range for the i and q channels is biased about v ref . it can go 1.25 volts about this point. signal to (noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the receive channel. the signal is the rms amplitude of the fundamental. noise is the rms sum of all amplitude of the fundamental. noise is the rms sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal-to-(noise+distortion) ratio for a sine wave is given by: signal to (noise + distortion) = (6.02n + 1.76) db
ad7002 C6C rev. b input clock timing 1 limit at parameter t a = C40 8 c to +85 8 c units description t 1 76 ns min clk1, clk2, aux clk cycle time t 2 30 ns min clk1, clk2, aux clk high time t 3 30 ns min clk1, clk2, aux clk low time transmit section timing limit at parameter t a = C40 8 c to +85 8 c units description t 4 10 ns min tx sleep hold time t 5 20 ns min tx sleep setup time t 6 24 t 1 ns min tx clk active after clk1 rising edge following 24 t 1 + 80 ns max tx sleep low t 7 48 t 1 ns tx clk cycle time t 8 24 t 1 ns tx clk high time t 9 24 t 1 ns tx clk low time t 10 0 ns min propagation delay from clk1 to tx clk 100 ns max 30 ns max t 11 30 ns max data setup time t 12 10 ns min data hold time t 13 0 ns min tx clk to tx sleep asserted for last tx clk cycle 2 23 t 1 ns max t 14 10 ns typ digital output rise time 3 t 15 10 ns typ digital output fall time 3 auxiliary dac timing limit at parameter t a = C40 8 c to +85 8 c units description t 16 10 ns min aux data setup time t 17 10 ns min aux data hold time t 18 25 ns min aux latch to sclk falling edge setup time t 19 20 ns min aux latch to sclk falling edge hold time t 20 50 ns max aux latch high to aux flag valid delay t 21 10 ns typ digital output rise time t 22 10 ns typ digital output fall time notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 t 13 specifies a window, that tx sleep should be asserted for the current tx clk to be the last prior to entering sleep mode. 3 digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 v. specifications subject to change without notice. (av dd = +5 v 6 10%; dv dd = +5 v 6 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted) (av dd = +5 v 6 10%; dv dd = +5 v 6 10%; agnd = dgnd = 0 v, f clk1 = f clk2 = 13 mhz; t a = t min to t max , unless otherwise noted) clk1, clk2, aux clk t 1 t 2 t 3 figure 1. clock timing to output pin +2.1v i ol 1.6ma i oh 200 m a c l 15pf figure 2. load circuit for timing specifications (av dd = +5 v 6 10%; dv dd = +5 v 6 10%; agnd = dgnd = 0 v, f aux clk = 13 mhz; t a = t min to t max , unless otherwise noted)
ad7002 C7C rev. b receive section timing 1 limit at parameter t a = C40 8 c to +85 8 c units description t 23 0 ns min rx sleep hold time after clk1, clk2 high t 24 25 ns min rx sleep setup time before clk1, clk2 high t 25 0 ns min rx sync to rx sleep asserted 2 39 t 1 ns max rate 0 15 t 1 ns max rate 1 t 26 rx clk active after clk1 rising edge following falling edge of rx sleep 32 t 1 + t 2 ns mode 0 31 t 1 + t 2 ns mode 1 t 27 rx clk cycle time 3 t 1 ns mode 0 2 t 1 ns mode 1 t 28 rx clk high pulse width 25 ns min mode 0 90 ns min mode 1 t 29 rx clk low pulse width 25 ns min mode 0 30 ns min mode 1 t 30 10 ns min propagation delay from clk1, clk2 high to rx clk high 30 ns max t 31 20 ns min rx sync valid prior to rx clk falling t 32 rx sync high pulse width t 1 ns mode 0 2 t 1 ns mode 1 t 33 rx sync cycle time 3 24 t 1 ns mode 0 rate 0 12 t 1 ns mode 0 rate 1 48 t 1 ns mode 1 rate 0 24 t 1 ns mode 1 rate 1 t 34 rx data valid after rx clk rising edge 5 ns max mode 0 t 1 + 5 ns max mode 1 t 35 5 ns max mode 0 only, propagation delay from rx clk rising edge to i/ q t 36 10 ns typ digital output rise time 4 t 37 10 ns typ digital output fall time 4 calibration and control timing limit at parameter t a = C40 8 c to +85 8 c units description t 38 25 ns min sleep to cal setup time t 39 608 t 1 ns min cal pulse width t 40 25 ns min rate, mode or three-state enable setup time notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 t 25 specifies a window, after rx sync which marks the beginning of i data, that rx sleep should be asserted for the subsequent iq data pair to be last prior to entering sleep mode. 3 see figure 2 for test circuit. 4 digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 v. specifications subject to change without notice. (av dd = +5 v 6 10%; dv dd = +5 v 6 10%; agnd = dgnd = 0 v, f clk1 = f clk2 = 13 mhz; t a = t min to t max , unless otherwise noted) (av dd = +5 v 6 10%; dv dd = +5 v 6 10%; agnd = dgnd = 0 v, f aux clk = 13 mhz; t a = t min to t max , unless otherwise noted)
ad7002 C8C rev. b circuit description transmit section the transmit section of the ad7002 generates gmsk i and q waveforms in accordance with gsm recommendation 5.04. this is accomplished by a digital gmsk modulator, followed by 10-bit dacs for the i and q channels and on-chip recon- struction filters. the gmsk (gaussian minimum shift keying) digital modulator generates i and q signals, at 16 3 oversam- pling, in response to the transmit data stream. the i and q data streams drive 10-bit dacs, which are filtered by on-chip bessel low-pass filters. guassian filter integrator cosine look up table sine look up table idata qdata 10 10 differential encoder tx data gmsk pulse shaping rom 16x oversampling figure 3. gmsk functional block diagram table i. truth table for the differential encoder tx data i tx data iC1 differentially encoded data 00 +1 01 C1 10 C1 11 +1 gmsk modulator figure 3 shows the functional block diagram of the gmsk modulator. this is implemented using control logic with a rom look up table, to generate i and q data samples at 16 times the transmit data rate. the transmit data (tx data) is first differentially encoded as specified by gsm 5.04 section 2.3 (table i). the gmsk modulator generates 10-bit i and q waveforms (inphase and quadrature), in response to the en- coded data, which are loaded into the 10-bit i and q transmit dacs. the gaussian filter, in the gmsk modulator, has an impulse response truncated to four data bits. when the transmit section is brought out of sleep mode (tx sleep low), the modulator is reset to a transmitting all 1s state. when tx sleep is asserted (tx sleep high), the trans- mit section powers down, with the i tx and q tx outputs con- nected to v ref through a nominal impedance of 80 k w . reconstruction filters the reconstruction filters smooth the dac output signals, providing continuous time i and q waveforms at the output pins. these are bessel low-pass filters with a cutoff frequency of approximately 300 khz. figure 5 shows a typical transmit filter frequency response, while figure 6 shows a typical plot of group delay versus frequency. the filters are designed to have a linear phase response in the passband and due to the reconstruction filters being on-chip, the phase mismatch between the i and q transmit channels is kept to a minimum. transmit section digital interface figure 4 shows the timing diagram for the transmit interface. tx sleep is sampled on the falling edge of clk1. when tx sleep is brought low, tx clk becomes active after 24 master clock cycles. tx clk can be used to clock out the transmit data from the asic or dsp on the rising edge and tx data is clocked into the ad7002 on the falling edge of tx clk. when tx sleep is asserted the transmit section is immediately put into sleep mode, disabling tx clk and power- ing down the transmit section. valid data t 4 t 5 clk1 (i) tx sleep (i) tx clk (o) tx data (i) t 7 t 12 t 6 t 11 valid data valid data t 8 t 9 t 10 t 13 note: (i) = digital input; (0) = digital output figure 4. transmit section timing diagram
ad7002 C9C rev. b 0.0 C60.0 1.00 + 07 C45.0 C55.0 1.00 + 04 C50.0 1.00 + 03 C30.0 C40.0 C35.0 C25.0 C20.0 C15.0 C5.0 C10.0 1.00 + 06 1.00 + 05 frequency C hz gain C db figure 5. transmit filter frequency response 0 C90 6.4 C70 C80 8.0 0 C60 C50 C40 C30 C20 C10 5.6 4.8 4.0 3.2 2.4 1.6 frequency C mhz magnitude C db gmsk spectrum test, dc to 6.4mhz. frequency resolution: 30.1514khz figure 7. typical spectrum plot of the transmit channel when transmitting random data (0 mhz to 6.4 mhz) 5 C5 C2 C4 C3 1 C1 0 2 3 4 peak phase trajectory error = 1.56 rms phase trajectory error = 0.79 peak phase trajectory error C degrees figure 9. typical plot of the transmit phase trajectory error 0.80 0.00 1.00 + 07 0.20 0.10 1.00 + 04 1.00 + 03 0.40 0.30 0.50 0.60 0.70 1.00 + 06 1.00 + 05 frequency C hz group delay C m s figure 6. transmit filter group delay 10 ?0 1000 ?0 ?0 100 ?0 0 ?0 ?0 ?0 ?0 ?0 0 900 800 700 600 500 400 300 200 frequency ?khz magnitude ?db gmsk mask gmsk spectrum figure 8. typical spectrum plot of the transmit channel when transmitting random data (0 mhz to 1 mhz) 1.27 1.21 1.22 1.24 1.23 1.26 1.25 i 2 + q 2 C voltage figure 10. typical plot of the composite vector magnitude
ad7002 C10C rev. b receive section the receive section consists of i and q receive channels, each comprised of a simple switched capacitor filter followed by a 12-bit sigma-delta adc. the data is available on a flexible serial interface, interfacing easily to most dsps. the data can be configured to be one of two formats and is also available at two sampling rates. onboard digital filters, which form part of the sigma-delta adcs, also perform critical system level filtering. their amplitude and phase response characteristics provide excellent adjacent channel rejection. the receive section is also provided with a low power sleep mode to place the receive sec- tion on standby between receive bursts, drawing only minimal current. switched capacitor input the receive section analog front end is sampled at 13 mhz by a switched capacitor filter. the filter has a zero at 6.5 mhz as shown in figure 11a. the receive channel also contains a digital low-pass filter (further details are contained in the following section) that operates at a clock frequency of 6.5 mhz. due to the sampling nature of the digital filter, the pass band is re- peated about the operating clock frequency and at multiples of the clock frequency (figure 11b). because the first null of the switched capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dbs (figure 11c), further simplifying the external antialiasing re- quirements. 6.5 13 19.5 mhz 6.5 13 19.5 mhz 6.5 13 19.5 mhz 0db 0db 0db C30db max front-end analog filter transfer function digital filter transfer function system filter transfer function a. b. c. figure 11. switched capacitor input sigma-delta adc the ad7002 receive channels employ a sigma-delta conversion technique that provides a high resolution 12-bit output for both i and q channels, with system filtering being implemented on-chip. the output of the switched capacitor filter is continuously sampled at 6.5 mhz (master clock/2) by a charge balanced modulator, and is converted into a digital pulse train whose duty cycle contains the digital information. due to the high oversam- pling rate, which spreads the quantization noise from 0 mhz to 3.25 mhz (f s /2), the noise energy contained in the band of interest is reduced (figure 12a). to reduce the quantization still further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (figure 12b). the digital filter that follows the modulator removes the large out-of-band quantization noise (figure 12c), while converting the digital pulse train into parallel 12-bit-wide binary data. the 12-bit i and q data is made available, via a serial interface, in a variety of formats. fs/2 3.25 mhz fs/2 3.25 mhz band of interest band of interest fs/2 3.25 mhz band of interest digital filter cutoff frequency = 122 khz noise shaping quantization noise a. b. c. figure 12. sigma-delta adc digital filter the digital filters used in the ad7002 receive section carry out two important functions. first, they remove the out-of-band quantization noise that is shaped by the analog modulator. sec- ond, they are also designed to perform system level filtering, providing excellent rejection of the neighboring channels. digital filtering has certain advantages over analog filtering. first, since digital filtering occurs after the a/d conversion process, it can remove noise injected during the conversion process. analog filtering cannot do this. second, the digital filter combines low passband ripple with a steep rolloff, while also maintaining a linear phase response. this is very difficult to achieve with analog filters. analog filtering can, however, remove noise superimposed on the analog signal before it reaches the adc. digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator, even though the average value of the signal is within limits. to allevi- ate this problem, the ad7002 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mv. filter characteristics the digital filter is a 288-tap fir filter, clocked at half the mas- ter clock frequency. the frequency response is shown in figure 14. the 3 db point is at 122 khz. due to the low pass nature of the receive filters, there is a settling time associated with step input functions. output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. hence the ad7002 digital filters have a settling time of 44.7 m s (288 3 2 t 1 ). when coming out of sleep, the digital filter taps are reset. hence data, initially generated by the digital filters, will not be correct. not until all 288 taps have been loaded with meaningful data
ad7002 C11C rev. b from the analog modulator, will the output data be correct. the analog modulator, on coming out of sleep, will generate mean- ingful data after 21 master clock cycles. 01...111 01...110 00...001 00...000 11...111 11...110 10...001 10...000 Cv fullscale +v fullscale v ref adc code v in , input voltage figure 13. adc transfer function for i and q receive channels calibration included in the digital filter is a means by which receive signal offsets may be calibrated out. calibration can be effected through the use of the cal and mzero pins. each channel of the digital low-pass filter section has an offset register. the offset register can be made to contain a value representing the dc offset of the preceding analog circuitry. in normal operation, the value stored in the offset register is sub- tracted from the filter output data before the data appears on the serial output pin. by so doing, the dc offset is cancelled. in each channel the offset register is cleared (twos complement zero) when cal is high and becomes loaded with the first digi- tal filter result after cal falls. this result will be a measure of the channel dc offset if the analog channel is switched to zero prior to cal falling. time must be provided for the analog circuitry and the digital filter to settle after the analog circuitry is switched to zero and before cal falls. the offset register will then be loaded with the proper representation of the dc offset. cal must be high for more than 608 master clock cycles (clk1, clk2). if the analog channels are switched to zero coincident with cal rising, this time is also sufficient to satisfy the settling time of the analog sigma-delta modulators and the digital filters. cal may be held high for an unlimited time if convenient or necessary. only the digital result following the fall of cal will be loaded into each offset register. after cal falls, normal operation resumes immediately. 10.00 C140.00 1000 C100.00 C120.00 100 0 C80.00 C50.00 C30.00 C10.00 900 800 700 600 500 400 300 200 0.00 C110.00 C130.00 C70.00 C90.00 C60.00 C40.00 C20.00 frequency C khz gain C db figure 14. digital filter frequency response the offset registers are static and retain their contents even during sleep mode (rx sleep 1 and rx sleep 2 high). they need only be updated if drifts in the analog dc offsets are experi- enced or expected. however, on initial application of power to the digital supply pins the offset registers may contain grossly incorrect values and, therefore, calibration must be activated at least once after power is applied even if the facility of calibration is not regularly used. table ii. truth table for the mode and rate pins mode rate data format output word rate 0 0 iq data i/ q 270.8 khz 0 1 iq data i/ q 541.7 khz 1 0 i data q data 270.8 khz 1 1 i data q data 541.7 khz the mzero pin can be used to zero the sigma-delta modula- tors if calibration of preceding analog circuitry is not required. each analog modulator has an internal analog multiplexer con- trolled by mzero. with mzero low, the modulator inputs are connected to the i rx and q rx pins for normal operation. with mzero high, both modulator inputs are connected to the v ref pin, which is analog ground for the modulators. if calibra- tion of external analog circuitry is desired, mzero should be kept low during the calibration cycle. rx sleep1 rx sleep2 cal rate, mode, three- state control t 39 t 38 40 t figure 15. calibration and control timing diagram
ad7002 C12C rev. b the offset registers have enough resolution to hold the value of any dc offset between 5 v. however, the performance of the sigma-delta modulators will degrade if full scale signals with more than 100 mv of offset are experienced. if large offsets are present, these can be calibrated out, but signal excursions from the offsets should be limited to keep the i rx and q rx voltages within 1.35 v of v ref . receive section digital interface a flexible serial interface is provided for the ad7002 receive section. four basic operating modes are available. table ii shows the truth table for the different serial modes available. the mode pin determines whether the i and q serial data is made available on two separate pins (mode 1) or combined onto a single output pin (mode 0). the rate pin determines whether i and q receive data is provided at 541.7 khz (rate 1) or at 270.8 khz (rate 0). when the receive section is put into sleep mode, by bringing rx sleep 1 and rx sleep 2 high, the receive interface will complete the current iq cycle before entering into a low power sleep mode. mode 0 rate i interface the timing diagram for the mode 0 rate 1 receive interface is shown in figure 16. it can be used to interface to dsp pro- cessors requiring only one serial port. when using mode 0, the serial data is made available on the rx data pin, with the i/ q pin indicating whether the 12-bit word being clocked out is an i sample or a q sample. although the i data is clocked out before the q data, internally both samples are processed together. rate 1 selects an output word rate of 541.7 khz, which is equal to the master clock (clk1, clk2) divided by 24. when the receive section is brought out of sleep mode, by bring- ing rx sleep 1 and rx sleep 2 low, (after 32 master clock cycles) the rx clk output will continuously shift out i and q data, always beginning with i data. rx sync provides a fram- ing signal used to indicate the beginning of an i or q, 12-bit data word that is valid on the next falling edge of rx clk. on coming out of sleep, rx sync goes high one clock cycle before the beginning of i data, and subsequently goes high in the same clock cycle as the last bit of each 12-bit word (both i and q). rx data is valid on the falling edge of rx clk and is clocked out msb first, with the i/ q pin indicating whether rx data is i data or q data. mode 0 rate 0 interface figure 17 shows the receive timing diagram when mode 0, rate 0 is selected. again i and q data are shifted out on the rx data pin, but here the output word rate is reduced to 270.8 khz, this being equal to master clock (clk1, clk2) divided by 48. once the receive section is brought out of sleep mode, (after 56 master clock cycles) the rx clk output becomes active and generates an rx sync framing pulse on the first rx clk. this is followed by 12 continuous clock cycles during which the i data is shifted out on the rx data pin. following this the rx clk remains high for 11 master clock cycles before clocking out the q data in exactly the same manner. rx data is valid on the falling edge of rx clk with the i/ q pin indicating whether rx data is i data or q data. mode 1 rate i interface figure 18 shows the timing for mode 1 rate 1 receive digital interface. mode 1 rate 1 gives an output word rate of 541.7 khz, but i and q data are transferred on separate pins. i data is shifted out on rx data (idata) pin and q data is shifted out on the i/ q (qdata) pin. rate 1 selects an output word rate of 541.7 khz (this is equal to the master clock divided by 24). when the receive section is brought out of sleep mode, by bring- ing rx sleep 1 and rx sleep 2 low (after 32 master clock cycles), the rx clk output will continuously shift out i and q data, on separate pins. rx sync provides a framing signal used to indicate the beginning of an i or q, 12-bit data word that is valid on the next falling edge of rx clk. on coming out of sleep, rx sync goes high one clock cycle before the begin- ning of i data, and subsequently goes high in the same clock cycle as the i and q lsbs. it takes 24 rx clks (excluding the first framing pulse) to complete a single iq cycle. idata and qdata are valid on the falling edge of rx clk and are clocked out msb first. mode i rate 0 interface figure 19 shows the receive timing diagram when mode 1 rate 0 is selected. mode 1 rate 0, again i and q data are transferred on separate pins. i data is shifted out on rx data (idata) pin and q data is shifted out on the i/ q (qdata) pin. the output word rate is reduced to 270.8 khz, this equal to master clock (clk1, clk2) divided by 48. once the receive section is brought out of sleep mode, and after 56 master clock cycles, the rx clk output becomes active and generates an rx sync framing pulse on the first rx clk. this is followed by 12 continuous clock cycles during which both the i and q data is shifted out on idata and qdata pins. fol- lowing this the rx clk remains high for 22 master clock cycles before clocking out the next iq data pair.
ad7002 C13C rev. b t 24 clk1, clk2 (i) rx sleep1 (i) rx sleep2 (i) rx clk (o) rx sync (o) rx data (o) t 23 t 28 t 29 t 30 t 32 t 31 t 34 t 33 t 35 t 35 note: (i) = digital input; (o) = digital output 26 27 tt i msb i lsb q msb q lsb i msb i lsb q msb q lsb 25 t i/q (o) figure 16. mode 0 rate 1 receive timing t 24 clk1, clk2 (i) rx sleep1 (i) rx sleep2 (i) rx clk (o) rx sync (o) t 26 rx data (o) t 23 t 27 t 28 t 30 t 31 t 33 t 35 t 35 t 29 i msb i lsb q msb q lsb t 34 i msb t 32 note: (i) = digital input; (o) = digital output i lsb q msb q lsb t 25 i/q (o) figure 17. mode 0 rate 0 receive timing t 24 clk1, clk2 (i) rx sleep1 (i) rx sleep2 (i) rx clk (o) rx sync (o) i data (o) q data (o) t 23 i msb t 29 i lsb t 30 t 31 i msb i lsb q msb q lsb q msb q lsb note: (i) = digital input; (o) = digital output t 27 t 28 t 32 t 33 t 34 t 34 t 25 t 26 figure 18. mode 1 rate 1 receive timing
ad7002 C14C rev. b auxiliary dacs three auxiliary dacs are provided for extra control functions such as automatic gain control, automatic frequency control or for ramping up/down the transmit power amplifiers during the beginning/end of a transmit burst. the three auxiliary dacs, aux dac1, aux dac2 and aux dac3, have resolutions of 9-, 10- and 8-bits, respectively. in addition to the three auxiliary dacs, the auxiliary section contains a digital output flag (aux flag) with three-state control. communication and sleep control of the auxiliary section is totally independent of either the transmit or receive sections. the ad7002 aux dacs are voltage mode dacs, consisting of rC2r ladder networks (figure 20 shows aux dac1 archi- tecture), constructed from highly stable thin-films resistors and high speed single pole, double throw switches. this design architecture leads to very low dac current during normal operation. however, the aux dacs have a high output impedance (typical 8 k w ) and hence require external buffering. the aux dacs have an output voltage range of 0 v to v ref C 1 lsb. each aux dac can be individually entered into low- power sleep mode, simply by loading all ones or all zeros to that particular aux dac. this does not affect the normal operation of aux dacs, as either of these two codes (all 0s = 0 m a, all 1s = 50 m a typical) represent the operating points for lowest power consumption. 2r r 2r r r 2r 2r agnd 2r db0 db1 db6 db7 db8 2r rr shown for all 1s on dac vref aux dac1 figure 20. auxiliary dac structure the digital aux flag output is available for any external logic control that may be required. for instance, the aux flag could be used to control the tx sleep pin, turning on 24 23 t clk1, clk2 (i) rx sleep1 (i) rx sleep2 (i) rx clk (o) rx sync (o) i data (o) q data (o) t i msb i lsb i msb i lsb t 30 t 31 q msb q lsb q msb q lsb note: (i) = digital input; (o) = digital output t 32 t 33 t 34 t 34 t 29 t 27 t 28 t 25 t 26 figure 19. mode 1 rate 0 receive timing the transmit section prior to ramping up (using one of aux dacs) the rf amplifiers. aux dac digital interface communication with the auxiliary section is accomplished via a three-pin serial interface, as the timing diagram in figure 22 illustrates. while aux latch is low, data is clocked into a 16-bit shift register via the aux data and aux clk pins. aux data is clocked on the falling edge of aux clk, msb first. the 16-bit shift register is organized as a data field (db0C db9) and as a control field (db10Cdb15). the data field is 8-, 9- or 10-bits wide, depending on the aux dac being loaded. the control field indicates which aux dacs are being loaded and also determines the state of the aux flag pin. when the shift register has been loaded, aux latch is brought high to update the selected aux dacs and the aux flag pin. the control bits are active high, and since a control bit has been assigned to each aux dac, this facilitates the simultaneous loading of more than one aux dac (with the same data). db10, db11 and db12 selected aux dac3, aux dac1 and aux dac2 respectively, and dbls deter- mines the logic state of aux flag while db14 determines whether the three-state driver is enabled. aux latch aux clk aux data 16-bit shift register auxdac select 9-bit aux dac1 10-bit aux dac2 8-bit aux dac3 aux dac1 aux dac2 aux dac3 db0Cdb9 db13 db15 db14 db12 db11 db10 en flag aux flag 10-bit aux latch 8-bit aux latch 9-bit aux latch figure 21. auxiliary section serial interface
ad7002 C15C rev. b pin function descriptions pqfp pin number mnemonic function power supply 37 av dd positive power supply for analog section. this is +5 v 10%. 38 agnd analog ground. 4, 15 dv dd positive power supply for digital section. this is +5 v 10%. 5, 16 dgnd digital ground. analog signal and reference 41 i tx analog output for the i (in-phase) channel. this output comes from a 10-bit dac and is filtered by a bessel low pass filter. the 10-bit dac is loaded with i data, which is generated by the gmsk modulator. 39 q tx analog output for the q (quadrature) channel. this output comes from a 10-bit dac and is filtered by a bessel low pass filter. the 10-bit dac is loaded with q data, which is generated by the gmsk modulator. 44 i rx analog input for i receive channel. 42 q rx analog input for q receive channel. 34 aux dac1 analog output voltage from the 9-bit auxiliary dac. this is a voltage mode dac with a high output impedance and hence should be buffered if used to drive moderate impedance loads. 36 aux dac2 analog output voltage from the 10-bit auxiliary dac. this is a voltage mode dac with a high output impedance and hence should be buffered if used to drive moderate impedance loads. 35 aux dac3 analog output voltage from the 8-bit auxiliary dac. this is a voltage mode dac with a high output impedance and hence should be buffered if used to drive moderate impedance loads. 40 refout reference output; this is 2.48 volts nominal. transmit interface and control 7, 11 clk1, clk2 master clock inputs for both the transmit and receive sections. clk1 and clk2 must be externally hardwired together and driven from a 13 mhz ttl compatible crystal. 3 tx clk clock output from the ad7002 which can be used to clock in the data for the transmit section. 2 tx data data input for the transmit section, data is clocked on the falling edge of tx clk. 1 tx sleep sleep control input for transmit section. when it is high, the transmit section goes into standby mode and draws minimal current. receive interface and control 13 mode digital control input. when high (mode 1), the i and q outputs are on separate pins (qdata and idata). when low (mode 0), i and q are on the same pin (rx data). 12 rate digital control input. this determines whether the receive section interface operates at a word rate of 541.7 khz or at a word rate of 270.8 khz. when high (rate 1), the output word rate is 541.7 khz. when low (rate 0), the output word rate is 270.8 khz. 18 rx data (idata) this is a dual function digital output. when the device is operating in mode 0, the rx data (both i and q) is available at this pin. when the device is operating in mode 1, only idata is available at this pin. voltage reference the ad7002 contains an on-chip bandgap reference that pro- vides a low noise, temperature compensated reference to the iq transmit dacs and the iq receive adcs. the reference is also made available on the refout pin and can be used to bias other analog circuitry in the if section. when both the transmit section and the receive section are in sleep mode (tx sleep and rx sleep asserted), the reference output buffer is also powered down by approximately 80% compatible crystal. t 17 aux clk (i) aux data (i) aux latch (i) aux flag (o) db15 db14 db1 db0 t 19 t 20 t 16 new aux flag old aux flag t 18 figure 22. auxiliary dac timing diagram
ad7002 C16C rev. b c1700bC0C6/97 printed in u.s.a. pqfp pin number mnemonic function 19 i/ q (qdata) t his is a dual function digital output. when the device is operating in mode 0, it indicates whether idata or qdata is present on rx data pin. in mode 1, qdata is available at this pin. 20 rx sync synchronization output for framing i and q data at the receive interface. 21 rx clk output clock for the receive section interface. 22 three-state this digital input controls the output three-state drivers on the receive section interface. when control it is high, the outputs are enabled. when low, they are in high impedance. 23 cal calibration control pin for digital filter section. when brought high, for a minimum of 608 master clock cycles, the receive section enters a calibration cycle. where i and q offset registers are up- dated, when the cal pin is brought low again, with offset values which are subtracted out from subsequent adc conversions. cal should remain low during normal operation. 29 mzero digital control input. when high the analog modulator input is internally grounded (i.e., tied to v ref ). mzero, in conjunction with cal, allows on-chip offsets to be calibrated out. low for normal operation. 27, 24 rx sleep 1 , power-down control inputs for receive section. when high, the receive section goes into rx sleep 2 standby mode and draws minimal current. rx sleep 1 and rx sleep 2 must be externally hardwired together for normal device operation. auxiliary interface and control 32 aux latch synchronization input for the auxiliary dacs shift register and aux out. 31 aux clk clock input for the auxiliary dacs 16-bit shift register. aux data is latched on the falling edge of aux clk while aux latch is low. 30 aux data data input for the aux dacs and the aux flag serial interface. 33 aux flag digital output flag, this can be used as a digital control output and is controlled from the auxiliary serial interface. test 8, 26 test l, test 2 test pins for factory use only. these pins should be left unconnected and not used as routes for other circuit signals. 14, 43 test 3, test 4 test pins. these must be tied to ground for normal device operation. outline dimensions dimensions shown in inches and (mm). plastic quad flatpack package (s-44) 1 44 34 33 23 22 12 11 top view pin 1 0.016 (0.41) 0.012 (0.30) 0.033 (0.84) 0.029 (0.74) 0.096 (2.44) max 0.037 (0.94) 0.025 (0.64) 0.398 (10.11) 0.390 (9.91) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 0.398 (10.11) 0.390 (9.91) 0.548 (13.925) 0.546 (13.875) 8 0.8

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